The present invention relates to a clock data recovery apparatus used in a data receiving system which receives data in a high-speed transmission system such as a chip or fiber-optic based communication system; and, more particularly, to a clock data recovery apparatus capable of stably operating in high frequency clocks.
As the communication system between chips is highly integrated with large capacity, demand on high and fast system integration increases. A transmission method which sends data information without clock synchronization has been used at a transmitting side because of the complexity of hardware, power consumption and cost. Accordingly, a receiving side of the communication system needs a clock signal capable of exactly recovering distorted data which are caused by a limited bandwidth on a channel thereof. At the time of transmitting mass data, this clock signal becomes more and more important, but an apparatus which stably creates the clock signal in synchronization with the receiving data can considerably influence the performance of the system. Accordingly, a clock data recovery apparatus is required to extract stable clock signals from the transmitted data.
FIG. 1 is a block diagram illustrating a conventional clock data recovery apparatus. Referring to FIG. 1, the conventional clock data recovery apparatus includes a phase locked loop (PLL) unit 110, a voltage controlled delay line (VCDL) 120, a phase detector 130, a charge pump 140 and a loop filter 150.
The phase locked loop unit 110 receives a reference clock signal and then outputs a stable clock signal with a constant frequency into the voltage controlled delay line 120.
The voltage controlled delay line 120 receives the clock signal from the phase locked loop unit 110 and controls an amount of delay of the clock signal based on an input voltage.
A timing information between the data and the clock signal, which are produced by the phase detector 130, is inputted into the voltage controlled delay line 120 via the charge pump 140 and the loop filter 150 and the voltage controlled delay line 120 controls a clock signals in order to make the data matched with the clock signal by delaying a clock signal based on the received timing information.
The phase detector 130 receives the clock signal and the data outputted from the voltage controlled delay line 120 and then compares a phase of the clock signal to a phase of the data. The result of the comparison, as an increment signal (UP) and a decrement signal (DOWN), is outputted to the charge pump 140. Also, the phase detector 130 outputs a recovered data which is synchronized with the clock signal and, in synchronization with the clock signal, a rising edge of the clock signal is arranged in the middle of the data pulse. That is, the phase detector 130, as shown in FIG. 1, functions as a retimer for recovering the data as well as the phase detection.
The charge pump 140 receives the increment signal (UP) and the decrement signal (DOWN) from the phase detector 130 and outputs current for executing a charging or discharging operation to the loop filter 150.
The loop filter 150 determines an amount of delay by outputting to the voltage controlled delay line 120 a voltage with a smooth variation which is converted by the current from the charge pump 140.
The clock data recovery apparatus controls the rising edge outputted from the phase locked loop unit 110 in such a manner that the rising edge is arranged in the middle of the data pulse. Accordingly, the finally recovered clock signal is outputted by the voltage controlled delay line 120 and the recovered data are outputted by the phase detector 130.
FIG. 2 is a block diagram illustrating the phase detector in the conventional clock data recovery apparatus of FIG. 1 and FIGS. 3A to 3C are timing charts showing an operation the phase detector of FIG. 2.
As shown in FIG. 2, the phase detector 130 includes a first D flip-flop DFF21 having an input terminal (D) to receive the data and a clock terminal (CLK) to which the clock signal is applied, a second D flip-flop DFF22 having an input terminal (D) to receive an output of the first D flip-flop DFF21 and a clock terminal (CLK) to which an inverted clock signal is applied, a first XOR gate XO21 for XORing the data and the output of the first D flip-flop DFF21, and a second XOR gate XO22 XORing the outputs of the first and second D flip-flops DFF21 and DFF22.
Referring to FIG. 3A, in case that the rising edge of the clock signal is arranged in the middle of the data pulse, the increment signal (UP) outputted from the phase detector 130 is out of phase with the decrement signal (DOWN) by a half-period. Accordingly, since the charging and discharging currents from the charge pump 140 are the same in the amount and the voltage which is applied to the voltage controlled delay line 120 is constant, the amount of delay in the voltage controlled delay line 120 does not vary. Namely, the locking is achieved.
Referring to FIG. 3B, in case that the rising edge of the clock signal lags behind the middle of the data pulse, the pulse width of the increment signal (UP) may be larger than that of the decrement signal (DOWN) (in this case, the decrement signal (DOWN) is maintained with a constant width). Accordingly, the amount of the charging current outputted from the charge pump 140 is more than that of the discharging current and the voltage which is applied to the voltage controlled delay line 120 is relatively high. Eventually, the voltage controlled delay line 120 makes the phase of the clock signal faster by controlling the amount of the delay.
Contrary to the phase of FIG. 3B, FIG. 3C shows a case that the rising edge of the clock signal leads the middle of the data pulse. In this case, the voltage which is applied to the voltage controlled delay line 120 is increased and the voltage controlled delay line 120 controls the phase of the clock signal to be arranged in the middle of the data pulse.
As mentioned above, the conventional data recovery apparatus employs the phase detector 130 as a means for comparing the phase of the clock signal with that of the data. However, with the increment of the frequency in the clock signal, the pulse width of the increment and decrement signals becomes narrower. The decrement in the pulse width of the increment and decrement signals makes a current flowing time of the charging and discharging currents short so that a variation in the voltage which is applied from the loop filter 150 to the voltage controlled delay line 120 is insignificant. This makes the data recovery apparatus unstable with a locking failure.
To overcome this problem, a clock dividing technique, which divides the clock signal at ½ or ¼ rate, is used; however, this technique still has a demerit in that it is difficult to obtain a sufficient pulse width of the increment and decrement signals.